Some information shared by Wei Zhejia
“This year marks TSMC’s 35th anniversary. When we started in 1987, we had a total of 258 employees and released 28 products covering 3 technologies; ten years later, we had 5,600 employees and released 20 technologies. 915 products; by 2022, we have 63,000 employees and will release 12,000 products covering 300 technologies.”
“From 2018 to 2022, the compound annual growth rate of 12-inch wafers (equivalent) exceeds 70%. In particular, we see a significant increase in the number of ‘big die’ products.” (>500mm²)
“In 2021, TSMC’s North American business segment shipped more than 7 million units and shipped more than 5,500 products. There are 700 new product tapeouts (NTO). This segment accounts for 65% of TSMC’s revenue.”
“Our gigafab expansion plans typically include the addition of two new ‘phases’ per year – as was the case in 2017-2019. In 2020, we opened six new phases, including our advanced packaging facility. 7 in 2021 A new phase, including fabs in Taiwan and overseas, has also added advanced packaging capacity. There will be five new phases in 2022, both in Taiwan and overseas.”
N2 Fab: Hsinchu Fab20
N3: Tainan Fab 18
N7 and N28: Kaohsiung Fab22
N28: Fab16 in Nanjing, China
N16, N28 and expertise: Fab23 in Kumamoto, Japan (2024)
Arizona’s N5 (2024)
“Statistically, TSMC owns 55% of the EUV lithography machine systems installed in the world”
“We will significantly expand capital equipment investment in 2022.” (The table below highlights the large increase in planned spending on capped equipment.)
“We are experiencing manufacturing pressure on mature process nodes. In 35 years, we have never increased capacity at a mature node after mass production at a subsequent node – but it is happening at Zhuangbian. We are investing to increase capacity on our 45nm process. (Later, in a Q&A session with another TSMC executive, a reporter asked if capacity expansion would be performed on other mature nodes such as 90nm or 65nm, and their response was: “No, expansion plans Currently only targeting the 45nm node.”)
“We continue to invest heavily in ‘smart manufacturing’ with a focus on precision process control, tool productivity and quality. Each gigafab handles 10 million dispatch orders per day and optimizes tool productivity. Each gigafab generates 70B data points per day for proactive monitor.”
For the first time at the workshop, a special “Innovation Zone” was allocated in the exhibition hall. Some of the recent offerings from startups are highlighted. TSMC said: “We have increased support investments to help small companies adopt our technology. There is a dedicated team focused on startups. Support for small customers has always been a focus. Maybe somewhere in this area will be the next Nvidia .”
12 key milestones for TSMC
In 1987, with the creation of the PurePlay business model, TSMC was established.
In 1999, TSMC became the first foundry to offer 0.18-micron copper technology.
2001 brought the first foundry reference design flow. TSMC spent a lot of money to create the huge EDA and IP ecosystem we enjoy today.
In 2011, TSMC brought HKMG 28nm into the fabless ecosystem. Other foundries are faltering at 28nm, so this is a record node for TSMC.
CoWos, the first heterogeneous 3DIC test vehicle, was launched in 2012.
In 2014, TSMC delivered the first fully functional FinFET network processor, ushering in the FinFET era dominated by TSMC today.
In 2015, TSMC passed the advanced 3DIC packaging technology InFo.
In 2018, TSMC made state-of-the-art logic technology (N7) available to everyone.
In 2020, TSMC leads the industry with N5 EUV-based logic technology.
In 2021, TSMC will launch N4P, N4X and N6RF.
In 2022, TSMC will launch the most advanced N3 process node covering a wide range of vertical markets. I think the N3 will also break the tapeout record within 5 years.
Last but not least, TSMC announced its next-generation process technology (N2) for the masses in 2022.
Process Technology Review
With a few exceptions discussed further, the underpinning technology roadmap presentation is somewhat routine — not a bad thing, but an indication that the previous roadmap is being successfully executed.
The roadmap update was presented twice, once as part of the technology agenda and once as part of TSMC’s platform solutions focus. Recall that TSMC specifically identified four “platforms” that each receive development investment to optimize process technology products, including: mobile; high performance computing (HPC); automotive; and IoT (ultra-low power). The abstract below combines the two presentations.
By the end of 2022, more than 400 NTOs, mainly in smartcell phoneand the CPU market
N6 provides transparent migration from N7, supporting IP reuse
N6RF will be the RF solution for upcoming WiFi 7 products
There is an N7HPC variant (not shown in the image above) that provides ~10% performance boost at overdrive VDD levels
For N6, logic cell-based blocks can be reimplemented in the new library to further improve performance, achieving a major logic density increase (~18%).
In the third year of production, more than 2 million wafers have been shipped using this process, reaching 150 NTOs by the end of 2022
Mobile customers come first, followed by HPC products
Roadmap includes ongoing N4 process enhancements
N4P base IP ready, interface IP available in Q3 2022 (to v1.0 PDK)
There is an N5HPC variant (not shown in the image above, about 8% performance gain, HVM will be in 2H22)
N3 and N3E
N3 to enter HVM starting in the second half of 2022
Mass production of N3E process variant in a year; TSMC expects widespread adoption of the process on mobile and HPC platforms
N3E Design Ready (v0.9 PDK) with high yield in standard 256Mb memory array qualification test site
N3E adds “FinFLEX” method option, three different cell libraries optimized for different PPA requirements
Note that N3 and N3E are somewhat anomalous from previous TSMC process roadmaps. N3E will not provide IPs that are transparently migrated from N3. The N3E product is a bit “fixed” as a major design rule change to the N3 was adopted to improve yield.
TSMC’s early adopter customers are pushing process PPA updates on aggressive timelines, whether incrementally compatible variants to existing baselines (e.g., N7 to N6, N5 to N4), or new nodes. The initial N3 process definition has a good NTO pipeline, but N3E will be the basis for future variants.
Based on nanosheet technology, target production date: 2025
Compared to N3E, N2 will provide about 10-15% performance boost (@iso-power, 0.75V) or about 25-30% reduction (@iso-perf, 0.75V); also note the graph above specified in the operating range down to 0.55V
N2 will support the back-end distribution network
By the way, TSMC is faced with the dilemma that the requirements of different platforms have such a wide range of power consumption, performance and area/cost targets. As mentioned above, N3E is using different libraries to solve these problems, combined with different numbers of fins that define the cell height. For the N2 library design, this design decision was superseded by a process technology decision regarding the overall number of vertically stacked nanosheets (with some allowable variation in device nanosheet width). In terms of nanosheet topologies, it will be interesting to see what TSMC chooses to offer for N2 to cover the mobile and HPC markets. (The image below, from TSMC’s early tech demo at VLSI 2022, depicts 3 nanosheets.)
Note: There are two emerging process technologies being adopted to reduce power transfer impedance and improve local routability – “buried” power rail (BPR) and “backside” power distribution (BSPDN) distribution). Initial investigations into delivering BPR have quickly expanded to address the roadmap for integrating a full BSPDN such as N2. However, it’s easy to confuse the two acronyms.
Sharing about special craftsmanship
TSMC defines the following products as the “Specialty Technologies” category:
1. Ultra-low power/ultra-low leakage (using ultra-high Vt device variants)
Requires special attention to ultra-low leakage SRAM bit cell design
N12e in production, N6e in development (focus on very low VDD model support)
Second, (embedded) non-volatile memory
1. Usually integrated with a microcontroller (MCU), usually in a ULP/ULL process
2 、 RRAM
Requires 2 additional masks, embedded in BEOL (much lower cost than eFlash’s 12 masks)
10K write cycles (endurance specification), ~10 years at 125C
22MRAM has been mass-produced, the focus is on improving tolerance
Mass production of 16MRAM for Automotive Grade 1 applications in 2023
3. Power Management IC (PMIC)
Bipolar CMOS-DMOS (BCD) based devices: 40BCD+, 22BCD+
Suitable for complex 48V/12V power domains
Requires extremely low equipment R_on
4. High pressure application(eg display driver, use N80HV or N55HV)
5. Analog/mixed-signal applications, requiring unique active and passive structures (e.g. precision thin film resistors and low noise devices using N22ULL and N16FFC)
6. MEMS(for motion sensor, pressure sensor)
Seven, CMOS image sensor(CIS)
N65 pixel size is 1.75um, N28 pixel size is 0.5um, transition to N12FFC
Eight, radio frequency (RF), wireless communications from mmWave to longer wavelengths; upcoming WiFi7 standard highlighted
“The transition from WiFi6 to WiFi7 will require a significant increase in area and power to support the increased bandwidth requirements – for example, 2.2X area and 2.1X job number. TSMC is certifying N6RF products, which will reduce power consumption compared to N16RF This will allow customers currently using N16RF to roughly maintain their existing power/area goals when developing WiFi7 designs.”
The diagram below illustrates how these specialized technologies become fundamental components of platform products such as smartphones and automotive products. Feature process nodes for these applications are also shown.
Although the focus of smartphone development tends to be on the main application processor, the following table highlights the extremely diverse requirements for specialized technical products and their associated functions. In the automotive world, the transition to a “zone control” architecture will require a new set of automotive ICs.
N3E and FinFLEX
TSMC specifically highlighted the newly released FinFLEX approach, which TSMC said will provide full-node scaling of N5.
With the expansion of FinFET technology nodes (i.e. from N16 to N10 to N7 to N5), the fin profile and drive current per micron have improved significantly. Standard cell library designs have evolved to include fewer pFET and nFET fins, which define the cell height (specified by the number of horizontal metal routing tracks). As shown above, the N5 library uses a 2-2 fin definition—that is, 2 pFET fins and 2 nFET fins to define the cell height. (N16/N12 use 3-3 configuration.)
The library definition for N3E faces several problems. The scale of performance improvement for pFET and nFET devices is not the same. Also, mobile and HPC platform applications are increasingly divergent in terms of their PPA (and cost) goals. Mobile products focus on circuit density to integrate more functions and/or reduce power consumption, while requiring less performance improvement. HPC is more focused on maximizing performance.
Therefore, N3E will provide three libraries, as shown in the image above:
2:1 ultra-low power library (rail height defined by 2 pFET:1 nFET)
2:2 efficient library
3:2 Performance Library
The image below, from TSMC’s FinFLEX website, illustrates the concept.
Now, integrating multiple libraries on a single SoC is nothing new. Over the years, processor companies have developed unique “datapath” and “control logic” library products targeting different goals: cell height, circuit performance, routability (i.e. maximum cell area utilization) and different logic products (e.g. , wide AND – OR gate for data path multiplexing). However, the physical implementation of a SoC design using multiple libraries relies on a consistent library for each design block.
Although the TSMC picture above also depicts one bank per block, the uniqueness of the FinFLEX approach is that multiple banks and multiple track heights will be mixed in a single block. Will support 2:1 plus 2:2 library and 2:2 plus 3:2 library combination.
“Enables different cell heights in a block (in separate rows) to optimize PPA. FinFLEX in N3E combines new design rules, new layout techniques, and significant changes to the EDA implementation flow,” TSMC said.
There will definitely be more information on FinFLEX and general design process changes. On the other hand, new methods are needed to:
Plan a percentage combination of two different row heights for a block
Target utilization percentage of cells in different bank rows for routability (including open cells for decap fill)
PDN “reduction” method for blocks with a significant percentage of low-power cells
The number of floorplanning iterations for the block (via physical synthesis) to reach closure
How synthesis will improve timing of critical signals
To improve timing for heavily loaded signals, synthesis typically updates cell assignments in the bank to the next higher drive strength—for example, NAND2_1X to NAND2_2X.
For FinFLEX, the second library provides additional options – for example, whether updates to NAND2_1X_2:2 use NAND2_2X_2:2 or NAND2_1X_3:2. However, if the latter is chosen, the new cells will need to be “rebalanced” to different rows in the block plan. The performance of these choices and the effective variation of input/output line loads are difficult to estimate during physical synthesis (not to mention that the specific RDLY and FDLY delay transitions of output rises and falls for different library cells may scale differently).
Cell selection options become more complex when considering the specific flop cells to be used, not only considering differences in clock-to-Q delays, but also setup and hold time characteristics and input clock loading. When would it be better to use different drive strengths (and place locally) for individual flip-flop bits in a register in the same bank than to rebalance register bits to rows corresponding to different bank selections?
3. Sub-block-level IP integration
Blocks typically contain many small hard IP macros, such as register files (usually provided by register file generators). How would these hard IP macros be designed and placed due to uneven cell row heights across a single block?
4. Timing/Power Optimization During Physical Design
Similar to the physical synthesis block construction option, cell selection will face difficult decisions during the timing and power optimization steps of the physical design flow. For example, if a cell can reduce its assigned drive strength to save power while still meeting timing, would a change in bank selection be considered to rebalance the rows? Will a change in cell position negate optimization?
V. Last but not least, will enabling N3E FinFLEX incur new EDA licensing fees?
(A few years ago, my previous employer’s CAD department manager went all the way to a license cost adder to enable place and route for multi-modal requirements. Given the large EDA investment required to support FinFLEX, history may repeat itself with the addition of license capabilities cost.)
The FinFLEX approach certainly offers some interesting options. It will be interesting to see how this approach evolves.
Analog Design Migration Automation
Finally, TSMC briefly highlighted their ongoing work in assisting designers in migrating analog/mixed-signal circuits and layouts to newer process nodes.
Specifically, TSMC defines a set of “analog cells” capable of taking existing schematics, remapping to new nodes, evaluating circuit optimization, and migrating layouts, including automatic placement and (PG + signal) routing.
The definition of the analog cell library for N5/N4 and N3E has been completed, and N7/N6 will be supported in the future. TSMC shows an example of an operational transconductance amplifier (OTA) through a migration flow.