@ExecutableFix and @Greymon55, just shared some interesting details on AMD’s next-generation Zen 5 EPYC Turin processor on Twitter.It is said that as the successor of the Genoa series, EPYC Turin will continue to use the SP5 platform, supplementing the unprecedented packaging design. Later this year, we are expected to be the first to see the evolution of stacked 3D chiplet design on EPYC Milan-X.
whenAMDWhen the Xiaolong Turin processor is officially unveiled a few years later, it can be speculated that this series of chips will integrate multiple CCDs and cache stacks on a single substrate.
In contrast, Genoa CPU has up to 96 cores, and Bergamo is considered an evolved version on the same Zen 4 architecture, which is said to have up to 128 cores.
In addition to the CPU and cache design, rumors also say that Turing is expected to usher in 256 cores, and with PCIe 6.0. If AMD intends to adopt a stacked X3D chiplet solution, it can even be pushed higher.
As for how to accommodate twice the number of cores of Genoa / Bergamo on the same SP5 platform, we are still full of curiosity about the legendary 192C / 384T and 256C / 512T EPYC Turin CPUs.
It is expected that in order to achieve this goal, AMD has two technical options. One is to double the number of cores of each CCD. At present, the single CCD of Zen 3 / Zen 4 can accommodate 8 cores.
If doubled to a single CCD / 16 cores, the EPYC server processor is expected to achieve the goal of 192/256 cores by stacking 12/16 CCDs.
In the previous rumors, MLID has introduced a new packaging layout, that is, it can support up to 16 sets of CCD on the SP5 platform. However, AMD has another less likely technical route, which is to continue to stack CCD on top of CCD.
In this way, even if each group of CCD maintains the same 8 cores, the overall design can still achieve multi-chip / 16 groups of CCD.
As for the thermal design power (TDP) of the chip, even if EPYC Turin uses TSMC’s most advanced 3nm process, the power requirement for double the core is quite exaggerated.
The upcoming 96-core EPYC Genoa CPU has an adjustable cTDP as high as 400W. If EPCY Turin’s cTDP hits a maximum of 600W, the SP5 socket (LGA 6096) seems to be able to withstand the peak power consumption of 700W (although it can only last for 1ms).
Gigabyte’s leaked information has confirmed various information about the next-generation platform. It is known that the number of SP5 pins is 2002 more contacts than the current LGA 4094.
If the duration is relaxed to 10ms, the peak power of the SP5 platform will fall to 440W (OCC peak 600W). After exceeding cTDP, the EPYC chip will restore the limit within 30ms.
Finally, the leaked AMD presentation also confirmed that the SoC of EPYC Genoa’s successor will support higher DDR5-6000 to 6400 memory (or refer to Bergamo / Turin).
If all goes well, AMD may launch EPYC Turin around 2024-2025, and will cooperate withIntelThe Diamond Rapids Xeon platform launched a more direct competition.