Advanced packaging is not the savior of the failure of Moore’s Law, nor is it a new technology path that is mutually exclusive with advanced technology. Its essential meaning is to tap the potential of the chip manufacturing process and reduce the delayed data transmission speed and the large amount of power consumption in traditional packaging. , It can be recovered to a great extent through technological and structural innovation.
Similar to the continuous iteration of the previous advanced technology, “advanced packaging” is actually a vague and long-term changing concept. The “advanced packaging” of each era means a technological system innovation. For example, when DIP, SOP, TSOP, QFP, LQFP and other technologies were regarded as traditional packaging in the past, BGA, CSP, FC, MCM (MCP) and other technologies would be called “advanced packaging.”
The “advanced packaging” that is widely mentioned nowadays is actually an upgrade transition from flat packaging to 2.5D/3D stacked heterogeneous integrated packaging technology.
Today’s “advanced packaging” concept is not proposed by packaging factories, it was first born in 2009 at TSMC. At that time, the TSMC team found that the lead line width on the traditional package substrate exceeded 50μm.As the data transfer volume between the logic chip and the memory chip becomes larger and larger, the high line width will cause about 40% of the entire chip’s transmission speed and 60% of the power consumption to be wasted.
If a silicon interposer is used to replace the traditional substrate, and the logic chip and memory chip are stacked and packaged, the lead line width can be reduced to less than 0.4 μm, and most of the lost transmission speed and power consumption can be recovered.
An industry insider told Jiwei.com,The team leader and TSMC’s chairman Zhang Zhongmou only communicated about the advanced packaging project for about an hour, and the latter gave a 400-person team deployment and a commitment of US$100 million in capital investment.Based on 3D stacking using silicon interposers, TSMC introduced CoWoS packaging technology in 2012, but it is difficult to promote due to the high cost. Then it launched the main targetcell phoneThe chip’s InFO packaging technology uses polyamide film to replace the silicon interposer in CoWoS, thereby reducing unit cost and packaging height.
CoWoS and InFO’s advanced packaging solutions not only add wings to TSMC’s advanced technology tiger, but also help it deeply bond with more and more customers. Among them, the most famous “battle” of TSMC’s advanced packaging technology is to eat it all.SamsungofAppleA series processor foundry orders.
As early as 2015, Apple’s A9 processor was also handed over to Samsung’s 14nm and TSMC’s 16nm foundry. And a year later, TSMC actually took all foundry orders for Apple’s A10 processor under the premise of using the 16nm process. From chamber resistance to dominance, only because TSMC fully enabled the self-developed InFO FOWLP packaging technology on the A10 chip, the A10 chip still achieved a 40% performance improvement and extended performance without upgrading the logic process.iPhoneStandby time.
Since 2016, while TSMC’s advanced technology is continuously exploring, advanced packaging technology is also constantly upgrading. The complementarity of the two makes Apple,AMD, Nvidia and other international giants have formed a long-term deep bond with TSMC.
Step by step to become the leader in wafer manufacturing, TSMC’s every move will obviously involve the nerves of all parties. The only ones that can compete with Intel and Samsung are also launching large-scale investment layouts in the advanced packaging field behind wafer manufacturing.
Who is the main force?
Taiwan Semiconductor Manufacturing Co., Ltd. has stepped up its packaging business. Samsung has followed up with X-Cube technology step by step. Intel has made architectural changes based on advanced packaging technology. Traditional packaging factories are in an awkward position.
Source: Samsung X-Cube technology
Is it because the packaging and testing plant can’t handle the “knife”, or is the fab’s requirements too high? Behind it is also related to the technical characteristics of advanced packaging itself.
From a technical point of view, all types of chips in traditional packaging are interconnected horizontally, while interconnects after stacking of chips in advanced packaging and when the chips are connected to the substrate down, a vertical interconnection method is required to improve the integration of the system. And effectiveness. At present, the industry mainly relies on TSV (Through Silicon Via) technology to achieve this.
In TSV technology, the silicon interposer is drilled by etching or laser, and then filled with conductive materials such as copper, polysilicon, tungsten, etc., so that the stacked chips can be vertically interconnected through the filled silicon channels. Compared with the previous IC packaging bonding and the use of bump superimposition technology, TSV can maximize the stacking density of the chip in the three-dimensional direction, the smallest size, and greatly improve the performance of chip speed and low power consumption. In the existing advanced packaging solutions, whether it is TSMC’s CoWoS, Intel’s Foveros 3D technology, and Samsung’s X-Cube technology, TSV technology is required.
It is precisely because TSV technology is indispensable for various advanced packaging systems nowadays, coupled with the inherent advantages of wafer fabs in silicon interposer manufacturing, the packaging divisions of mainstream wafer fabs are coming one after another.
“Due to the particularity of technology and structure, advanced packaging requires both wafer manufacturing processes and conventional packaging processes. This also means that whether it is a fab or a packaging plant, if you want to enter the advanced packaging business, you need to learn from each other’s strengths. “A senior in the field of advanced packaging told Jiwei.”Since the number of disciplines involved in the wafer manufacturing industry and the complexity of process engineering are much higher than those of the packaging industry, the technical difficulty of learning packaging for a wafer manufacturing plant is much lower than that for a packaging plant to learn wafer manufacturing.“
Since it is a cross-field technology, can fabs and packaging plants continue to establish a long-term cooperative relationship in the field of advanced packaging?
An insider in a Taiwanese fab pointed out that the fab and packaging plant cannot establish a long-term cooperative relationship in the field of advanced packaging. The reasons include the following two points:
The first is the uneven yield rate and the difficulty of dividing responsibilities.It is difficult for wafer fabs and packaging plants to achieve uniform yield. If the wafer fab completes production and then transports it to the packaging plant for advanced packaging, the final yield of the chip needs to be jointly responsible for both parties, and because the two have their own yield rates Because of the difference, the fab and the packaging plant cannot cooperate for a long time under the situation of unequal yield.
Secondly, the improvement of chip performance by advanced packaging is obvious, and fabs are racing around with this, and are looking forward to forming a deep bond with more major customers.That is to say, when the industry-leading advanced packaging technology is mastered, the fab can usher in more and more stable foundry orders. Therefore, it is difficult for mainstream fabs to pass such an important advanced packaging task to packaging and testing plants.
The “invasion” of fabs will inevitably squeeze the future business growth space of packaging plants to a certain extent. Therefore, first-line packaging plants outside mainland China have also begun to compete in the field of advanced packaging. However, the “advanced packaging” mentioned by the packaging factory is more generalized, which will be flip-chip (FC), chip-scale packaging (CSP), system-in-package (SiP), and wafer-level packaging (WLP) based on materials such as glass. The technology is also called advanced packaging.
Although the advanced packaging technology promoted by the packaging plant has progressed, it still has a gap with the advanced packaging led by the wafer plant. Take the wafer-level packaging of the packaging factory as an example. In the rewiring layer of the silicon interposer, not only the number of Die per unit area is higher, but the line width limit (1.8/1.8μm and below) is also much lower than that of organic materials or Glass (4/4μm and above). This also means that advanced packaging technology based on silicon interposers in fabs will have a higher D2D interconnect density.
The aforementioned Taiwanese fab insider told Jiwei: “Ultra-low line width is the ultimate meaning of advanced packaging, and currently only fabs can reduce the line width to less than 1.8/1.8μm on the silicon interposer.As for why it must be 1.8/1.8μm, this is mainly because more and more chip makers choose to combine CPU/GPU/TPU with one or more high-bandwidth memory (HBM) for advanced packaging, and the industry currently HBM is aligned with the line The minimum requirement for width is 1.8/1.8μm. “
Big stage and bigger stage
Half of the technological innovation of advanced packaging is embodied in 2.5D/3D stacking, and the other half is also embodied in heterogeneous integration. Both are indispensable.
If we only talk about stacking, as early as 2006, Samsung used TSV technology to stack and package 8 2Gb NAND Flash into the same chip. And Xilinx, an early customer of TSMC’s CoWoS technology, only used four identical FPGA chips to stack. TSMC’s advanced packaging team has mixed joys and worries about this. The good news is that customers are willing to adopt this new technology, but the worry is this homogeneous stacking. It is not possible for CoWoS to show its full strength until the first customer who uses CoWoS technology for heterogeneous integration is ushered inHuaweiHiSilicon, TSMC’s advanced packaging process has finally begun to become famous.
Therefore, heterogeneous integration based on 2.5D/3D stacking is a complete advanced packaging structure. With the blessing of these two features, high-end chips are a big stage for advanced packaging.
The vigorous development of new applications such as 5G, autonomous driving, artificial intelligence, and high-performance computing has spawned massive amounts of data. These data need not only be calculated inside the chip, but also need to be stored. DDR has been difficult to provide the high bandwidth required by chip manufacturers, and the IO bottleneck is getting more and more serious. Therefore, chip manufacturers choose to combine and package CPU/GPU/TPU with one or more high-bandwidth memory (HBM) so that the bandwidth is no longer restricted by The interconnection number of chip pins brings lower delay and power consumption.
Currently, AMD, NVIDIA,IntelThe high-end chips of other chip manufacturers have adopted advanced packaging technology, and according to industry insiders, at present, almost all high-end AI chips in TSMC’s current chip will choose CoWoS technology.
Looking to the future,The future trend of Chiplet will create a bigger stage for advanced packaging.VeriSilicon’s chairman Dai Weimin has stated on many occasions in public that not every chip requires cutting-edge technology, because not every company can afford the cost of 7nm and 5nm processes, so Chiplet mixes die with different process nodes. The new form of sealing is one of the important trends of future chips.
Weimin Dai emphasized that packaging and interfaces are very important to Chiplet. TSMC’s CoWoS technology and Intel’s Foveros 3D packaging technology have laid the foundation for Chiplet’s development.
According to the Omdia report, the global market for Chiplet processor chips is growing rapidly, and is expected to reach 5.8 billion U.S. dollars by 2024 and more than 57 billion U.S. dollars in 2035.
Stand on the starting line
In the advanced packaging defined by the packaging and testing plant, mainland manufacturers such as Changjiang Electronics Technology Co., Ltd. are advancing side by side with major manufacturers such as ASE and Amkor. However, at the advanced packaging level under the leadership of the foundry discussed in this article, currently only TSMC, Intel and Samsung can provide a complete advanced packaging platform in the world, and the foundry in mainland China is still standing outside the starting line.
It is worth mentioning that the leading foundry manufacturers in mainland China seem to have released positive signals. Zhang Xin, senior vice president of SMIC, pointed out when referring to its six major platforms at the IC WORLD conference a few days ago: “The company’s advanced packaging platform will provide full coverage Interposer solutions in the 2.5D field, and 3D IC will provide HBM/near memory computing solutions.”
The layout of advanced packaging in fabs has become the general trend. For SMIC, which has suffered severe containment in advanced technology, the development of advanced packaging is not only to conform to the trend of the industry, but also to stretch the battle line and improve its own business level.
Advanced packaging will not only create new opportunities for SMIC and other mainland fabs, but also bring challenges and development opportunities to upstream material, equipment and EDA manufacturers. Taking equipment as an example, the layout of advanced packaging platforms in fabs such as SMIC requires a large number of packaging and testing equipment, such as placement machines, wire bonding equipment, etc., and due to supply chain security considerations, domestic equipment is bound to be the future The main suppliers, the coordinated development of upstream and downstream can achieve success.
It is worth mentioning that the local equipment manufacturer Huafeng Technology has achieved some gains in the field of advanced packaging. Its placement machine equipment has passed the technical verification of TSMC, Changjiang Electronics Technology and other manufacturers, and has obtained ASE, Sipin, and Tongfu Bulk purchases from head manufacturers such as Microelectronics.
In addition, in terms of EDA, advanced packaging is a new field, and there is no mature design analysis solution before. The use of traditional and disjointed point tools and processes will bring huge challenges to design convergence, and it will be a complete signal and power supply. The demand for sexual analysis has also exploded with vertically stacked chips. therefore,Advanced packaging requires an unprecedented EDA platform, which is a breakthrough opportunity for domestic EDA manufacturers.
A few days ago, at the annual user conference held by the local EDA manufacturer Core and Semiconductor, the company’s CEO Ling Feng once introduced that supporting advanced technology and advanced packaging has always been the direction of core and semiconductor products. The company’s IRIS, iModeler, and Metis series products are all able to completebeautifulSupport advanced technology and packaging.
It is not difficult to see that local suppliers have taken the lead in “smelling” this important technology trend of advanced packaging, and have successively started related business layouts. Upstream suppliers are the first to stand on the starting line, followed by fabs. This healthy and industrial logic development method has laid the foundation for China’s local advanced packaging technology.
For a long time, wafer manufacturing has always been a backward link in China’s semiconductor industry, but packaging technology has the smallest gap between the mainland semiconductor industry and the world’s top technology. After international mainstream fabs entered advanced packaging, the gap in packaging technology has also been further widened. In this situation, while catching up with advanced technology, local fabs must keep pace with mainstream international manufacturers, otherwise China’s semiconductor industry will face the crisis of dual backwardness in manufacturing and packaging technologies in the future. (Proofreading/Talking)