Both fabs and packaging factories seek to obtain a higher proportion of the value of the industry chain in the chiplet era. In China, Changdian Technology launched the TSV-less advanced packaging solution XDFOI, leading the development of the industry; Tongfu Microelectronics, through its excellent wafer-level packaging capabilities, bound AMD to achieve rapid growth.
Source: Changjiang Securities “Chiplet Technology: Advanced Packaging, Who Owns the Ups and Downs”
Author: Yang Yang, Zhong Zhihua, Han Zijie
01. Chiplet chip heterogeneity optimizes efficiency at the manufacturing level
In fact, the original conceptual prototype of Chiplet came from Gordon Moore’s 1965 paper “Cramming more components onto integrated circuits”; Gordon Moore not only proposed the famous Moore’s Law in this paper, but also pointed out that “building large systems with smaller functions is more For economy, these functions are individually packaged and interconnected.”
In 2015, Dr. Zhou Xiuwen from Marvell proposed the concept of MoChi (Modular Chip) at the ISSCC conference, paving the way for the emergence of Chiplet. We believe that the development of the modern information technology industry is not an exploration of the unknown process, but a demand-driven technology upgrade. The emergence of Chiplet technology is an inevitable choice for the industrial chain to optimize production efficiency.
A computer is a device capable of instructing and automatically performing any arithmetic or logical operation in a series according to a series of instructions. In daily life, any electronic system we use can be regarded as a computer, such as: computer,cell phone, tablet and evenMicro-wave oven, remote control, etc. all contain the computer system as the core control device.
The emergence of Chiplet is inseparable from two major trends:
1) The heterogeneity and integration of computer systems are getting higher and higher
In order to facilitate the understanding of why the industry must choose Chiplet, this report starts from the perspective of computer architecture. This report will first clarify an important development idea of computer architecture-heterogeneous computing. Just like the modern economic system, in order to pursue higher output efficiency, the modern economic system has produced an extremely large and complex industrial division of labor system, and the re-division of labor in computer systems is heterogeneous computing.
The emergence of GPU and DPU is to make up for the shortcomings of CPU in graphics computing, data processing, etc., so that CPU can focus on logic judgment and execution, which is the computer system (System). The refined division of labor also makes the entire system huge. In small computing devices, only different chips can be integrated into one chip to form a SoC (System on Chip).
▲ The concept of SoC (System on Chip)
As computers take on more and more processing work in modern human life, the heterogeneous trend of computer architecture will become more and more obvious, and the required chip area will become larger and larger, and chips such as power management ICs will also be required. Logic chips are heterogeneously integrated, and SoC, as a single chip, has limited area and processing methods, so SoC is not the ultimate solution for heterogeneity.
2) The problem of data path bandwidth and delay between chips has been solved by the industry
The job of a chip is to execute instructions and process data, and the interconnection between chips requires huge bandwidth and ultra-low latency. Since the area of a single chip cannot be increased indefinitely, it is a natural idea to disassemble a chip into multiple chips, manufacture them separately and then package them together. The interconnection between chips requires the construction of a powerful data path, that is, ultra-high frequency, ultra-large bandwidth, and ultra-low latency. Advanced packaging technology represented by TSMC CoWoS technology has also solved it.
▲ HBM2 based on advanced packaging provides the chip with a high-speed bandwidth of 307GB/s
March 2022,appleThe company released the M1 Ultra chip, which uses the UltraFusion package architecture, interconnected by two M1 Max dies. Architecturally, the M1 Ultra uses a 20-core central processing unit consisting of 16 high-performance cores and 4 energy-efficient cores. Compared to 16-core CPU chips on the market in a similar power consumption range, the M1Ultra offers 90% better performance. The high-speed interconnection of the two M1 Max is the key to Apple’s chip leadership. Apple’s UltraFusion architecture uses a silicon interposer to connect multiple chips and can transmit more than 10,000 signals at the same time, thus achieving up to 2.5TB/s low-latency processor interconnection bandwidth .
▲ The internal structure of the M1 chip in the past dynasties, the M1 Ultra is made of two M1 Max spliced together
In order to alleviate the “storage wall” problem, AMD took the lead in adopting a 3D stacked L3 cache in its Zen 3 architecture Ryzen 7 5800X3D desktop processor, allowing the CPU to access up to 96MB of L3-level cache, greatly improving the chip’s computing efficiency.
▲AMD Zen 3 chipset
3) Heterogeneous integration + high-speed interconnection has shaped Chiplet, a milestone in the chip industry
In summary, Chiplet itself is not a technological breakthrough, but a milestone jointly shaped by a number of technological iterative advancements. Chip leading companies still have the right to speak; therefore, Chiplet technology will not bring too much direct impact and changes to the industry in the short term. , but in the long run, it will definitely change the ecology of the global integrated circuit industry. At the same time, because Chiplet has mature technical support in design, manufacturing, packaging and other links, its advancement will also be very rapid.
▲ Chiplet is the integration of PCB and the deconstruction of SoC
Technology serves demand, and the emergence of Chiplets alleviates the contradiction between the dependence of computing power on the number of transistors and the bottleneck of wafer manufacturing. As mentioned earlier, the demand that led to the emergence of Chiplet technology determines the size of its impact on the industry. With the increasing demand for computing power in modern data processing tasks, in essence, the core of computing power improvement is the increase in the number of transistors.
asIntelOne of the founders, Gordon Moore, stated in the original model that the number of transistors on a single chip cannot be increased indefinitely, neither from a technical perspective nor from a cost perspective; therefore, the industry is working on increasing transistor density at the same time. , is also trying other software and hardware methods to improve the operating efficiency of the chip, such as: heterogeneous computing, distributed computing and so on.
▲ The relationship between the production unit price of transistor devices and the number of transistors on the chip
Chiplet is an extension of heterogeneous computing, which mainly solves the efficiency problem at the chip manufacturing level. As the process shrinks, the core
There are two major bottlenecks in chip manufacturing: 1) After 28nm, the cost performance of transistors in high-process chips will no longer improve; 2) The cost of chip design has increased significantly, and the sunk cost of advanced-process chip design is unacceptably high.
▲ The manufacturing cost per million chips of each process will not be reduced after the 28nm node
▲ Rapidly rising cost of advanced process chip design (million US dollars)
On how Chiplets improve the efficiency of design, production, and the impact on EDA, IC design and other industries:
(1) Based on the area advantage of small chips, Chiplet can greatly improve the yield of large chips, improve the efficiency of wafer area utilization, and reduce costs;
(2) Based on the flexibility of the chip composition, after the SoC is chipletized, different cores/chips can be manufactured separately by selecting the appropriate process, and then packaged through advanced packaging technology. Integrated manufacturing on a single wafer can greatly reduce the manufacturing cost of the chip;
(3) Based on the reusability and verified characteristics of the small chip IP, the large-scale SoC is decomposed into modular chips according to different functional modules, reducing repeated design and verification links, which can reduce the complexity and design of the design. cost and improve product iteration speed.
▲ Compared with 32-core SoC, Chiplet can greatly reduce the cost of chip manufacturing
Although the overall manufacturing cost has been optimized, as advanced packaging plays a more important role in the chiplet manufacturing process, packaging and testing companies may benefit deeply from the chiplet trend. The field of chiplet packaging is currently showing a situation where a hundred flowers are blooming. The core of Chiplet is to achieve high-speed interconnection between chips, while taking into account the rewiring after multi-chip interconnection. Therefore, the UCIe Alliance does not impose strict restrictions on its members in terms of specific packaging methods. According to the Chiplet white paper released by the UCIe Alliance, the UCIe Alliance supports four mainstream packaging methods on the market, namely:
1) Standard package: The metal connection between the chips is buried in the package substrate. 2) Use a silicon bridge to connect the chips and embed the silicon bridge into the package substrate, such as Intel EMIB solution. 3) Use a silicon interposer (Si Interposer) to connect and rewire the chip, and then package the silicon interposer onto the substrate, such as TSMC CoWoS solution. 4) Use a fan-out interposer for rewiring, and only use a silicon bridge connection at the chip connection, such as the ASE FOCoS-B solution.
▲ 4 chiplet packaging methods recommended by the UCIe Alliance
At present, with its advantages in the foundry field, TSMC’s CoWoS technology platform has served many customers, and it has also iterated many batches. It is mainly realized by etching TSV through holes on the silicon wafer. The technical difficulties are mainly to achieve the alignment of high aspect ratio through holes and high density pins. After the Die and Interposer are produced, they are encapsulated by the packaging factory.
The core technology of Chiplet at the packaging level is the interconnection between chips. The data transmission speed and delay between chips that it can achieve are the keys to technological competitiveness. At the same time, the stability and universality of the solution will also profoundly affect its long-term development space. .
02. There are two camps in the global pattern, and the heroes are competing
The advanced packaging technology that Chiplet relies on has not yet been unified in the industry chain, and is mainly divided into the fab camp and the packaging plant camp: the fab camp is mainly based on silicon wafer processing to achieve interconnection, which can provide higher-speed connections and more advanced technology. Good scalability; the packaging factory camp strives to reduce the demand for silicon wafer processing and propose cheaper and more cost-effective solutions.
TSMC: Integrate the 3DFabric platform to achieve rich topology combinations. In terms of 2.5D and 3D advanced packaging technology, TSMC has integrated 2.5D and 3D advanced packaging related technologies into a “3DFabric” platform, which can be freely selected by customers. The front-end technology includes a 3D integrated chip system (SoIC InFO-3D), and the latter Segment assembly test related technologies include 2D/2.5D integrated fan-out (InFO) and 2.5D CoWoS series family.
▲ TSMC 3DFabric platform
In terms of 2.5D, TSMC provides two major solutions including CoWoS and InFO. Among them, CoWoS includes three packaging methods: CoWoS-S, CoWoS-R and CoWoS-L.
CoWoS-S uses a silicon interposer, using a silicon wafer as an interposer to connect chiplets. Compared with other solutions, the large-area silicon wafer as an interposer can provide higher density chip interconnection, but it is also more expensive.
▲ TSMC CoWoS-S architecture
CoWoS-R uses an organic interposer to reduce costs. Its packaging scheme is the same as that provided by some packaging and testing factories. The organic interposer can achieve lower interconnection density.
CoWoS-L uses small silicon “bridges” inserted into organic interposers and uses silicon wafers only in the interconnecting portion of the chip for high-density interconnects between adjacent chip edges. This way of implementing interconnection is between CoWoS-R and CoWoS-S in terms of cost and performance.
On the InFO side, after precise (face-down) placement by TSMC on a temporary carrier, the chip is encapsulated in an epoxy “wafer” and a redistribution interconnect layer is added to the reconstructed wafer surface, connecting the package bumps directly To the redistribution layer, it mainly includes three topologies: InFO_PoP (mainly used for mobile platforms), InFO_oS (mainly used for HPC customers) and InFO_B (an alternative to InFO_PoP).
▲ TSMC InFO_PoP and InFO_B (bottom only) architecture
▲ TSMC InFO_OS architecture
TSMC’s more advanced vertical chip stacking 3D topology package family is called “system-on-chip” (SoIC), which utilizes direct copper bonding between chips with finer pitches.
▲ TSMC 3D chip stacking SoIC
Samsung: The 3D IC packaging solution strengthens the chiplet foundry industry layout. Samsung started the research and development of packaging technology since 1990, and currently realizes the evolution of high-end packaging technology through SiP. The main technology trends are summarized as follows.
▲ History of Samsung Electronics’ packaging layout
In August 2020, Samsung announced the X Cube 3D packaging technology (the full name is extended cube, which means extended cube). For chip interconnection, the mature through-silicon via TSV process is used. At present, X Cube has been able to stack SRAM chips on the logic chips produced by Samsung’s 7nm EUV process, which makes it easier to expand the capacity of SRAM and shorten the signal connection distance to improve the speed of data transmission and improve energy efficiency. I-Cubes have since been released to place one or more logic dies and multiple HBM dies horizontally on a silicon interposer for heterogeneous integration.
▲ Samsung Electronics 3D IC Solutions
ASE: The FOCoS solution strives to reduce silicon and costs. ASE’s FOCoS offers a silicon bridge technology for chiplet integration, called FOCoS-B (Bridge), which utilizes tiny silicon wafers with routing layers as in-package interconnects between chiplets, such as graphics Compute Chip (GPU) and High Bandwidth Memory (HBM). The silicon bridge is embedded in the fan-out RDL layer, a 2.5D packaging solution that can eliminate the use of a silicon interposer.
FOCoS’s silicon bridges provide ultra-fine-pitch interconnects in packages that can address memory bandwidth bottleneck challenges in systems. The advantage of FOCoS-B compared to 2.5D packaging using a silicon interposer is that only the area where the two chiplets are connected together uses silicon, which can significantly reduce cost.
▲ ASE FOCoS solution
Amkor: Deep layout TSV-less process. In terms of Amkor, the company launched SLIM and SWIFT solutions in 2015; and continues to carry out technical layout, with 2.5D / 3D TSV packaging capabilities.
▲ Amkor SLIM / SWIFT solution
TSV-less processes can be used to create advanced 3D structures. Both SLIM and SWIFT solutions use TSV-less technology, which simplifies the PECVD and CMP processes for 2.5D TSV silicon interposers.
Taking the SWIFT (Silicon Wafer Integrated Fan-Out Technology) solution as an example, the solution adopts RDL first technology, RDL line width and line spacing capability ≤ 2um, μbump pitch 40um, SWIFT package can realize multi-chip integrated 3D POP package and no TSV (TSV) -Less) HDFO high-density fan-out package with cost advantage, suitable for high-performance CPU/GPU, FPGA, Mobile AP and Mobile BB, etc.
The unique properties of 3D SWIFT are due in part to the fine pitch capabilities associated with this innovative wafer-level packaging technology. It enables the application of proactive design rules, distinct from traditional WLFO and laminate-based packaging, and can be used to create advanced 3D structures to address the rising demands of IC integration in emerging mobile and networking applications.
Changdian Technology: Domestic packaging leader, leading the TSV-less route. Changdian Technology focuses on key application areas, and has industry-leading semiconductor advanced packaging technologies (such as SiP, WL-CSP, FC, eWLB, PiP, PoP and XDFOI series, etc.) and mixed-signal/RF integrated circuit testing and resource advantages, and achieve mass production, able to provide tailor-made technical solutions for the market and customers.
▲ The history of Changdian Technology
The XDFOI solution is expected to be mass-produced in 2022H2. Compared with 2.5D TSV, XDFOI has higher performance, higher reliability and lower cost. XDFOI is a packaging technology with 2.5D TSV-less as the basic technology platform. In terms of design, this technology can realize 3-4 layers of high-density traces, and the minimum line width/line spacing can reach 2μm, which can realize multiple layer wiring layer.
In addition, the extremely narrow pitch bump interconnect technology is adopted, and the package size is large, which can integrate multiple chips, high-bandwidth memory and passive devices. Changdian Technology has completed ultra-high-density wiring and started the customer sample process. It is expected to be mass-produced in 2022H2. The key application areas are high-performance computing such as FPGA, CPU/GPU, AI, 5G, autonomous driving, and smart medical care.
Changdian Technology’s through-silicon-via-free fan-out wafer-level high-density packaging technology can replace TSV technology with stacked via technology (Stacked VIA) in the silicon interposer (Si Interposer). This technology can realize multi-layer RDL redistribution layers, 2×2um line width spacing, 40um extremely narrow bump interconnection, and multi-layer chip stacking.
In addition, the extremely narrow pitch bump interconnect technology used in XDFOI technology can also achieve a package size of 44mm × 44mm and support the integration of multiple chips, high-bandwidth memory and passive devices inside. These advantages can provide cost-effective, high-integration, high-density interconnection and high-reliability solutions for chip heterogeneous integration.
▲ Changdian Technology XDFOI 2.5D technical features
Advanced packaging and testing technology covers the 4nm process, breaking through the top packaging process nodes in China. Changdian Technology announced in July 2022 that it has made new breakthroughs in the field of packaging and testing technology, realizing the packaging of mobile phone chips made by 4nm process, as well as the integrated packaging of CPU, GPU and RF chips. As an advanced silicon node technology, 4nm chips are also part of the introduction of Chiplet packaging. As one of the top technology products in the field of integrated circuits, 4nm chips can be used in smartphones, 5G communications, artificial intelligence, autonomous driving, and applications including GPU, CPU, FPGA, High-performance computing, including products such as ASICs.
Tongfu Microelectronics: Binding AMD, wafer-level packaging helps Chiplet. The leader in the global packaging and testing industry, and advanced packaging cultivates high-quality customers. Tongfu Microelectronics was established in 1997 and listed on the Shenzhen Stock Exchange in 2007, mainly engaged in the integrated business of integrated circuit packaging and testing. In 2021, the global OSAT Zhongtongfu Microelectronics ranks fifth in the world and seventh in advanced packaging.
At present, the company’s technology layout is progressing smoothly, and mass production of Chiplet products has begun. In terms of process nodes, 7nm products have achieved mass production, and 5nm products have completed research and development. Benefiting from the company’s continuous efforts in packaging and testing technology, the company currently cooperates with AMD, NXP, TI, Infineon, ST, MediaTek, Zhanrui, Weir, Zhaoyi Innovation, Changxin Storage, Yangtze River Storage, Chichuang North It has established good cooperative relations with other domestic and foreign head customers in various segments. In 2021, the business scale of domestic customers will increase by more than 100%. Continue to stabilize the business ballast.
▲ The history of Tongfu Microelectronics
At present, the company has built a domestic top 2.5D / 3D packaging platform (VISionS) and a super-sized FCBGA R&D platform, and completed the development of high-level rewiring technology.
▲ The current packaging technology progress of Tongfu Microelectronics
For Chiplet, Tongfu Microelectronics provides two solutions of wafer-level and substrate-level packaging, of which wafer-level TSV technology is an important part of the chiplet technology path. Most of the WLP wafer-level packaging process is to package the wafer as a whole, and then cut and slice after the packaging is completed.
Wafer-level packaging is to package multiple bare dies together in the form of a shared substrate between chips. It is mainly used for the packaging of high-performance large chips. It uses a sub-micron silicon interposer to integrate multiple chips into a single package with TSV technology. can significantly reduce material cost, using carrierless technology, after chip-to-wafer bonding and gap filling, the entire wafer is overmolded and flipped due to backside TSV exposure, and is directly maintained by epoxy mold resin .
Chiplet believes that in the post-Moore era, Chiplet has received widespread attention due to its high performance, low power consumption, high area utilization and low cost, and high hopes are placed on the “economic benefits” of continuing Moore’s Law. In the post-Moore era, Chiplet chip design can lower the threshold for large-scale chip design, bringing huge development opportunities to China’s integrated circuit industry.