A preliminary analysis of AMD “Zen 4” chip, transistor count, cache size and latency details
‘Skyjuice’ shows the first notes of the ‘Zen 4’ core, revealing its large branch prediction unit, enlarged micro-op cache, TLB, load/store units, and a dual-pump 256-bit FPU capable of AVX-512 . A quarter of the die area of this core is also taken up by 1MB of dedicated L2 cache.
Chiakokhua (aka retired engineer) posted a table detailing the various caches and their latencies, comparing them to the caches of the “Zen 3” cores. asAMDAs revealed by Mark Papermaster at the Ryzen 7000 launch event, the company has moved the core’s micro-op cache fromChekaB is enlarged to 6.75KB. The size of the L1I and L1D caches remains at 32KB; while the size of the L2 cache is doubled. The enlargement of the L2 cache increases latency slightly, from 12 to 14 cycles. The latency of the shared L3 cache has also increased, from 46 cycles to 50 cycles. The reorder buffer (ROB) of the scheduling phase has been enlarged from 256 entries to 320 entries. The size of the L1 branch target buffer (BTB) was increased from 1KB to 1.5KB.
Despite the higher transistor count, the Zen 4’s CCD is slightly smaller than the Zen 3’s, thanks to the conversion of the 5nm (TSMC N5 process) process. The size of the new generation CCD is 70mm², while the CCD size of “Zen 3″ is 83mm². The Zen 4” CCD has a transistor count of 6.57 billion, a 58% increase over the “Zen 3” CCD and its 4.15 billion transistor count.
The cIOD (Client I/O Chip) has a large part of the innovation. It’s built on the 6nm (TSMC N6) node, which is a huge leap from the GlobalFoundries 12nm node used by the cIOD of Ryzen 5000 series processors. It also absorbs some of the power management features of the Ryzen 6000 “Rembrandt” processors. In addition to the DDR5 memory controller and a PCI-Express Gen 5 root complex, this CIOD also features an iGPU based on the RDNA2 graphics architecture. The new 6nm cIOD measures 124.7mm square, compared to the slightly larger 124.9mm square for the Ryzen 5000 series.
“Raphael” multi-chip modules feature one CCD for 6- and 8-core SKUs, and two CCDs for 12- and 16-core SKUs. “Raphael” is built in the Socket AM5 package. AMD is rumored to be preparing a thin BGA packaged “Raphael” codenamed “Dragon Range” for high-performance notebook platforms. These processors will be available in various 45W, 55W, and 65W TDP options, providing a variety of options for high-end gaming notebooks.